The present invention relates broadly to an RF phase shift apparatus, and in particular to a digital phase shift apparatus.
The state of the art of digital phase shifters is well represented and alleviated to some degree by the prior art apparatus and approaches which are contained in the following U.S. Patents:
U.S. Pat. No. 4,398,161 issued to Lamb et al on Aug. 9, 1983;
U.S. Pat. No. 4,458,219 issued to Vorhaus on Jul. 3, 1984;
U.S. Pat. No. 4,471,330 issued to Naster et al on Sep. 11, 1984;
U.S. Pat. No. 4,599,585 issued to Vorhaus et al on Jul. 8, 1986;
U.S. Pat. No. 4,647,789 issued to Upadhyayula on Mar. 3, 1987; and
U.S. Pat. No. 4,652,883 issued to Andricos on Mar. 24, 1987.
The Lamb et al reference discloses a phase shifting circuit comprising a quadrature hybrid for splitting a source of signals into two paths, with an amplifier in each path and a summing hybrid for recombining the outputs from the amplifiers to produce a resultant signal. Phase shift adjustment is achieved by independently varying the gain control voltage of each amplifier.
The Vorhaus reference illustrates a phase shifter which includes three cascade interconnected phase shift stages. Each stage includes a quadrature coupler and a pair of field effect transistors (FET), having a pair of gates, a drain, and a source, connected in a common (grounded) source configuration. The drain of each FET is coupled to an input port of the quadrature coupler to provide two signal paths having an electrical pathlength difference corresponding to a 90.degree. differential phase shift. In the third stage, a length of transmission line is coupled between a drain of one of the FET's and one input port of the coupler to provide a signal path having an electrical pathlength corresponding to 180.degree. phase shift.
The Naster et al reference discloses a digital phase bit for microwave operation which comprises a pair of FET switches and at least three transmission lines. The FETs when operated in a digital switching mode, present a small impedance when on and a high impedance when off. Each of two of the transmission lines exhibits a series inductive impedance over the operating frequency band and shunts a FET switch, two shunt combinations being interconnected by the third transmission line.
The Vorhaus et al reference discloses a n-bit digitally controlled phase shifter for controlling the phase of an applied signal over the range of 0.degree. to 360.degree. includes n, cascade interconnected phase shifter stages. Each phase shifter stage is formed on a semi-insulating substrate having a pair of field effect transistors and a pair of transmission lines formed therein.
The Upadhyayula reference describes a continuously variable phase shifter for the phase range from 0.degree. to 90.degree., switchable phase shifters switchable between 0.degree. and 90.degree. and a continuously variable phase shifter for the phase shift range of 0.degree. to 360.degree.. Each of the phase shifters relies on dual gate FET devices to provide the required phase shift in a compact structure while providing sufficient gain to avoid signal losses through the phase shifter.
The Andricos reference describes a radar pulse shifter which includes several phase shift devices whose phase shift angles can be added together, which produces a minimal VSWR and an accurately controllable total phase shift.
Digital phase shifters are essential to phased array radars and communication systems. Digital phase shift is commonly accomplished by path length switching, phase reversal reflection or propagation constant modulation. Typically, PIN switching diodes, varactor diodes or FETs are employed as the switching element to change the phase of an RF signal from one state to another. There is shown in FIGS. 1 through 3 examples of prior art digital phase shift apparatus. Loss of signal strength is a major concern. The circuit attenuation is often compensated by an amplifier external to the phase shifter. An alternative approach is to integrate dual gate FET amplifiers into the phase shifter circuit to provide gain and digital phase shift simultaneously. For example, the circulator coupled PIN diode path length modulator, shown in FIG. 1a, provides 180 phase change when the PIN diode alternates between a forward biased low impedance state to a high impedance reverse bias state. The circulator 100 has three ports, 1, 2 and 3. The switching termination 101 which is connected to port 2 may comprise a PIN diode, an FET or similar switching device. Similar phase shifters can be constructed using a branch line coupler and two PIN diodes as shown in FIG. 1b. The branch line coupler 102 has four ports 1 through 4. Switching terminations 103 are connected to branch line coupler 102 ports 2 and 3. The switching terminations 103 which are connected to ports 2 and 3 may comprise a PIN diode, an FET or similar switching device. A second type of digital phase shifter makes use of the loading along a transmission line to change the propagation constants. An example of the switching load phase shifter is shown in FIG. 2. The characteristic impedance, Zo of load 104 may be changed by utilizing switching units 105, 106. The switching units 105, 106 are respectively connected to impedance B1, B2. The switching units 105, 106 which are connected to the load 104 may comprise a PIN diode, an FET or similar switching device. A third phase shifter type which is shown in FIG. 3, is called a switching line phase shifter because the line length of the signal path is switched, resulting in a change in phase delay. A common feature of these phase shifters is the circuit loss that is associated with the components. A substantial loss in signal strength or system sensitivity can result if multi-bidigital phase shift is required.
A phase shifter with signal gain is highly desirable. One way to accomplish this objective is to insert amplifiers in the phase shifter circuits. Alternatively, transistor amplifiers can be employed as path length switches with gain. The digital phase shifter that is shown in FIG. 4 employs two dual gate FETs connected in a common source configuration. The RF signal is amplified by the first or the second FET depending on which one is cutoff by controlled bias voltages applied to the second gates. The difference in signal path is the distance between the two transistors. The gate electrode must be terminated with a matched load to prevent high VSWR at the line segment connecting the gate electrodes otherwise no net phase shift can be realized.
The common source dual gate FET phase shifter, as shown in FIG. 4, relies on the control voltage which is applied to the second gate to switch the signal path. Substantial signal attenuation is encountered in the connecting delay line section between the two FETs. In addition, the dual gate FET configuration places a heavy burden on the wafer fabrication process control. A substantial reduction in processing yield can be achieved by going from circuits using single gate devices rather than dual gate structures. This gain in processing yield will be especially noticeable if the gate length is in the submicron dimensions.
The present invention provides a low cost, compact integrated phase shifter with signal gain. This digital phase shift apparatus will have particular application in air borne radar, and SDI related microwave and millimeterwave system programs.